搜索资源列表
modelsim_example_c
- modelsim仿真,大量vhdl程序,验证,很有价值!-The ModelSim Simulation, a large number of VHDL procedures, validation, great value!
cam
- 经过ModelSim验证过的cam程序,基于VHDL语言编写-After ModelSim verified cam program, based on VHDL language
FPGA_trainning2013A
- 在EDA实验课上面,自己编写的NCO程序,可以产生出比较真实的正弦波、三角波以及锯齿波,用VHDL程序编写,有modelsim仿真textbench程序-On EDA experiment, oneself write the NCO program, can produce more real sine wave, triangular wave and sawtooth wave with VHDL programming, have the modelsim simulation text
yimaqi_beh
- 8位计数器作业中的behavioral描写,没有带testbench,已经通过-1. Construct VHDL models for 74-139 dual 2-to-4-line decoders using three descr iption types, i.e., behavioral, dataflow and structural descr iptions. Synthesize and simulate these models respectively in the en
ise_c8051
- r8051(c8051)IP源码,使用VHDL编写。整个工程通过ISE13.2实现,附带完整testbench,并实例化了rom和ram,可以运行c代码。工程内包含modelsim的仿真脚本,可以观测程序运行时的内部硬件工作情况。-r8051 (c8051) IP source code, the use of VHDL. The whole project is realized by ISE13.2, with complete testbench, and examples of the
myfir
- VHDL设计的FIR滤波器,有Matlab设计文件,Quartus II工程以及Modelsim仿真结果和说明文件-VHDL design FIR filters, Matlab design documents, Quartus II project and Modelsim simulation results and documentation
I2C
- I2C总线控制器的VHDL代码、ISE工程文件、ModelSim仿真环境等-I2C bus controller VHDL code, ISE project file, ModelSim simulation environment
fli_c_vhdl_cosimulation
- using modelsim foreign language interface for c-vhdl cosimulation and for simulator control on linux x86
heap
- program heap in vhdl realise in modelsim
CPU
- 我是2014级复旦的研究生。这是一个8位的CPU设计VHDL实现。本CPU基于RISC架构,实现了cpu的基本功能如:加减乘除运算,跳转等。此外,里面有一个17位的ROM区,是存储指令的。你可以写出一段17位的指令代码,并放入ROM区,该CPU即可自动运行出结果。压缩包里是源代码和我们当时的设计要求。本源代码的最后调试时在地址0 17是放入的斐波纳契数字(Fibonacci Numbers)指令。通过modelsim仿真即可看到结果。-I am a 2014 graduate of Fudan
triangular_vhd
- This the triangular wave generation vhdl code to check the wave form in modelsim simulator-This is the triangular wave generation vhdl code to check the wave form in modelsim simulator
md5
- md5算法的vhdl实现,并配有测试用例,并没有使用任何xilinx的library,用modelsim se进行仿真-md5 algorithm based on fpga in vhdl
texio-user-method
- T E X T I O 在V H D L 仿真与磁盘文件之间架起了桥梁,使用文本文件扩展V H D L 的仿真功能。本文介绍 TEXTIO 程序包,以一个加法器实例说明TEXTIO 的使用方法,最后使用ModelSim 对设计进行仿真, 并分析仿真结果。-TEXTIO between VHDL simulation and bridges the gap between the disk file, use a text file extension of VHDL simulation
hough_5289
- hough变换的vhdl程序设计,测试没有任何问题,可以执行,开发工具quartus,modelsim-hough transform with fpga and vhdl ,good tested and you can use it happily
log_generator
- log10 generator in vhdl. simulated in Modelsim
DDSN
- quartus II 13.0 DDS工程文件,采用VHDL编写,可输出正交两路正弦信号。可以直接用modelsim-alter 仿真-quartus II 13.0 DDS project file, using VHDL written two orthogonal sinusoidal output signals. Can be simulated directly modelsim-alter
串并转换
- vhdl实现串并转换,其中附有源程序和testbench程序,可以用modelsim仿真
Assignment1_153070052
- Booth_multiplier in VHDL It will work in modelsim or GHDL
simProcessorEx
- 一个简单微处理器内核的VHDL程序,包含源代码(位于Source目录内)及ModelSim仿真代码(位于testBench目录内)。使用该内核进行一个功能验证程序(位于simProc_test目录内)-a simple processor core program and test code based on VHDL language
boxingfashengqi
- 波形发生器的源代码,有正弦波,三角波,锯齿波,方波。modelsim仿真,包含testbench仿真代码,testbench用的verilog编写,波形发生器源代码用的VHDL编写。-Waveform generator source code, sine, triangle, sawtooth, square wave. modelsim simulation, testbench simulation code contains, verilog write testbench use, w